From $50 educational projects to $7,000 production chips
Tiny Tapeout is the perfect entry point into the world of silicon. For just $50-300, you can get your first design manufactured on real silicon using the same GF180MCU process technology that powers wafer.space.
Starting price for your first silicon
Same process as wafer.space
"Tiny Tapeout democratizes chip design education, making it accessible to students, hobbyists, and engineers worldwide."
Tiny Tapeout uses a shared tile system that makes silicon manufacturing more accessible. Instead of requiring a full chip design, you create a small digital circuit that gets placed alongside dozens of other designs on a single silicon wafer.
| Process: | GF180MCU (180nm) |
| Tile Size: | 160×100 μm |
| Digital I/O: | 8 pins per design |
| Clock: | Up to 50 MHz |
Both platforms will offer GF180MCU process as an option, allowing knowledge and designs to transfer from education to low-volume production.
Start with shared tiles to learn and validate concepts, then transition to dedicated chips for low-volume production.
Access to the same design tools, PDKs, and community knowledge across both educational and production platforms.
At FSiC 2025, Matt Venn announced that Tiny Tapeout has secured funding to add GF180MCU support to their infrastructure. GF180MCU offers a cost-effective alternative to their existing SKY130 and iHP130 processes. Future GF180MCU tapeouts will be run through wafer.space.
From education to production, we've got you covered
Start with Tiny Tapeout to understand chip design fundamentals and get your first design on silicon.
Use the shared tile space to test concepts and validate your designs before committing to larger projects.
Move to wafer.space for low-volume production with a dedicated chip starting at $7,000 for bare dies or $8,500 for wire-bonded chips.
Continue with wafer.space for low-volume production runs and ongoing manufacturing needs.
Understanding the technical differences to choose your optimal path
| Specification | Tiny Tapeout Tiles | wafer.space Full Chip |
|---|---|---|
| Silicon Area | 160×100 μm (0.016 mm²) |
3.88×5.07 mm (~20 mm²) |
| Design Freedom | Digital logic only Pre-defined I/O constraints |
Complete chip design Custom I/O, analog, mixed-signal |
| I/O Pins | 8 digital pins Shared through multiplexer |
Custom pad frame Hundreds of I/O options |
| Clock Speed | Up to 50 MHz Shared clock distribution |
Process-limited Custom clock networks |
| Packaging | PCB with test setup Educational/prototyping |
Raw die Custom packaging available |
| Quantity | 1 chip (shared) Your design is 1 tile |
500-1,000 dies Low-volume production |
| Best For | Learning, prototyping, validation Students, hobbyists, concept testing |
Low-volume production, complex designs Startups, companies, advanced projects |
Offer silicon education from concept to low-volume production. Students can gain real chip design experience.
Prototype affordably before committing to larger investments. Validate your concepts on real silicon.
Turn passion projects into viable products. Experience the thrill of seeing your designs come to life.
Gain hands-on experience with real silicon. Stay current with modern chip design methodologies.
Join thousands of designers who have already started their path to silicon success.
Begin with Tiny Tapeout to get your first design on silicon and learn the fundamentals.
Join Tiny TapeoutReady for low-volume production? Transition from Tiny Tapeout to wafer.space.
Get Started with wafer.space